By Piyush Wairale (M.Tech, IIT Madras) · Former Instructor, IIT Madras BS Degree Programme · Mentor to 20,000+ GATE aspirants · Updated November 2026

GATE CSE 2027 Digital Logic Syllabus (Official, IIT Madras)

Section 2 of the CS paper, as released by IIT Madras: Boolean algebra and minimization (algebraic technique, Karnaugh map, tabular method). Design of combinational and sequential circuits. Number representation and arithmetic (fixed and floating point).

See the complete paper structure in the GATE CS 2027 syllabus and exam pattern guide.

Topic-wise Weightage and Priority

Boolean Algebra and K-Map Minimisation

Key identities: absorption (A + AB = A), consensus (AB + A’C + BC = AB + A’C), De Morgan ((A+B)’ = A’B’), and the duality principle. NAND and NOR are each functionally complete. With n variables there are 2²ⁿ distinct Boolean functions; self-dual functions number 2²ⁿ⁻¹.

K-map rules: group 1s in powers of two, make every group as large as possible, use as few groups as possible, and remember the map wraps around its edges. A prime implicant is a group that cannot be enlarged; an essential prime implicant covers at least one minterm no other PI covers. Don’t-care cells may be used only when they make a group bigger. The tabular (Quine-McCluskey) method does the same systematically by merging minterms that differ in one bit.

Combinational Circuit Design

A 2ⁿ:1 multiplexer has n select lines and can implement any function of n+1 variables (with one variable on the data inputs). Building a 2ⁿ:1 MUX from 2:1 MUXes needs 2ⁿ − 1 of them. An n:2ⁿ decoder plus an OR gate implements any n-variable function in SOP form. A full adder gives Sum = A ⊕ B ⊕ C_in and Carry = AB + C_in(A ⊕ B). A ripple-carry adder’s delay grows linearly with the number of bits; a carry-lookahead adder trades extra gates for constant-depth carry generation.

Sequential Circuit Design

A mod-N counter needs ⌈log₂N⌉ flip-flops. An n-bit ring counter has n states; an n-bit Johnson (twisted ring) counter has 2n states. For counter questions, trace the state table clock by clock from the given initial state rather than guessing the pattern.

Number Representation and Arithmetic

Fixed point: an n-bit 2’s complement number ranges from −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1. Overflow in signed addition happens only when both operands have the same sign and the result’s sign differs (equivalently, carry into MSB ≠ carry out of MSB). Sign-magnitude and 1’s complement both have two representations of zero.

Floating point (IEEE 754): single precision = 1 sign bit, 8 exponent bits (bias 127), 23 fraction bits; double precision = 1, 11 (bias 1023), 52. A normalised value equals (−1)^S × 1.F × 2^E−bias. Exponent all 0s means zero or denormal; all 1s means infinity or NaN.

Five GATE-Style Problems, Solved

Q1 (MCQ). Minimise F(A,B,C) = Σm(0, 2, 4, 5, 6).
Solution: Minterms 0, 2, 4, 6 all have C = 0, giving C’. Minterms 4 and 5 give AB’. Minimal SOP: F = C’ + AB’.

Q2 (NAT). What is the most negative integer in 8-bit 2’s complement?
Solution: −2⁷ = −128 (the range is −128 to +127).

Q3 (NAT). Decode the IEEE 754 single precision pattern: sign 0, exponent 10000001, fraction 0100…0.
Solution: Exponent = 129 − 127 = 2. Mantissa = 1.01₂ = 1.25. Value = 1.25 × 4 = 5.0.

Q4 (NAT). How many 2:1 multiplexers are needed to build a 16:1 multiplexer?
Solution: 8 + 4 + 2 + 1 = 15.

Q5 (NAT). How many distinct states does a 4-bit Johnson counter cycle through?
Solution: 2n = 8.

Common Mistakes to Avoid

Forgetting K-map wrap-around, which hides larger groups at the edges and corners.

Using a don’t care that does not enlarge a group, which adds an unnecessary term.

Confusing carry-out with overflow in signed 2’s complement addition.

Forgetting the hidden 1 (and the bias) when decoding IEEE 754 numbers.

Assuming a counter’s sequence instead of tracing the flip-flop inputs clock by clock.

2 to 3 Week Preparation Strategy

Week 1: Boolean algebra, K-maps up to 4 variables, Quine-McCluskey, and number systems with 2’s complement and IEEE 754.

Week 2: Combinational circuits (MUX, decoder, adders) and sequential circuits (flip-flops, counters, state tables). Solve 10 years of GATE CS Digital Logic questions.

Week 3: Take the Digital Logic subject-wise tests in the GATE CSE 2027 Test Series, then move straight to Computer Organization & Architecture, which builds on the same foundations.

FAQs: GATE CSE 2027 Digital Logic

GATE CSE 2027: All Subject-wise Guides

1. Engineering Mathematics · 2. Digital Logic · 3. Computer Organization & Architecture · 4. Programming & Data Structures · 5. Algorithms · 6. Theory of Computation · 7. Compiler Design · 8. Operating System · 9. Databases (DBMS) · 10. Computer Networks

Full paper overview: GATE CS 2027 Syllabus, Exam Pattern & Cutoff. Practise all ten subjects in one place with the GATE CSE 2027 Test Series.