GATE CSE 2027 Computer Organization and Architecture: Syllabus, Weightage, Cache, Pipelining & Solved Problems
COA is the numerical-heavy heart of GATE CSE. Here is every syllabus topic, the formulas that solve 90% of the questions, worked cache and pipeline numericals, and a focused plan.
By Piyush Wairale (M.Tech, IIT Madras) · Former Instructor, IIT Madras BS Degree Programme · Mentor to 20,000+ GATE aspirants · Updated November 2026
Quick Answer
• Computer Organization and Architecture (COA) is Section 3 of GATE CSE 2027 and typically carries 8 to 9 marks.
• The two topics that decide your COA score are cache memory mapping and instruction pipelining with hazards; both appear almost every year as NAT numericals.
• Other syllabus topics: instruction sets and addressing modes, ALU design, hardwired vs microprogrammed control, memory interfacing and hierarchy, and I/O (interrupts and DMA).
• COA rewards speed and accuracy under time pressure, which is exactly what the GATE CSE 2027 Test Series by Piyush Wairale trains.
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Official syllabus · Weightage · ISA & addressing modes · ALU & control unit · Memory & cache · I/O, interrupts, DMA · Pipelining · Solved problems · Strategy · FAQs
GATE CSE 2027 COA Syllabus (Official, IIT Madras)
Section 3 of the CS paper: Instruction set and addressing modes. Design of arithmetic and logic unit (ALU). Design of control unit (hardwired and microprogrammed). Memory interfacing and hierarchy: performance, cache memory mapping. I/O interface (interrupt and DMA). Instruction pipelining, pipeline hazards.
Complete paper details: GATE CS 2027 syllabus and exam pattern.
Topic-wise Weightage and Priority
| Topic | Typical question | Priority |
|---|---|---|
| Cache memory & hierarchy | Tag/index/offset bits, hit ratio, AMAT, hit/miss sequence | Very high |
| Pipelining & hazards | Speedup, total cycles, stalls, forwarding, branch penalty | Very high |
| Addressing modes & ISA | Effective address, instruction format bit fields | Medium |
| I/O, interrupts, DMA | DMA transfer time, % CPU time consumed, cycle stealing | Medium |
| Control unit & ALU | Control word size, horizontal vs vertical microprogramming | Medium |
Instruction Set and Addressing Modes
Know where the operand lives in each mode: immediate (in the instruction), direct (EA = address field), indirect (EA = M[address field]), register, register indirect (EA = R), indexed (EA = address + index register), base (EA = base register + displacement) and PC-relative (EA = PC + offset, where PC already points to the next instruction). Instruction-format questions ask you to split a fixed word into opcode, register and address fields: with 2k registers a register field needs k bits.
ALU and Control Unit Design
The ALU builds on the adders and multiplexers from Digital Logic. A hardwired control unit generates signals with combinational logic: fast but hard to modify. A microprogrammed control unit stores control words in control memory: flexible but slower. In horizontal microprogramming each control signal has its own bit (wide words, high parallelism); in vertical microprogramming signals are encoded (narrow words, needs decoders). A group of n mutually exclusive signals encodes into ⌈log2(n+1)⌉ bits when a no-signal option is needed.
Memory Hierarchy and Cache Mapping
| Mapping | Address split |
|---|---|
| Direct mapped | Tag | Line index (log2 lines) | Block offset (log2 block size) |
| k-way set associative | Tag | Set index (log2(lines/k)) | Block offset |
| Fully associative | Tag | Block offset (no index) |
Key formulas: AMAT = hit time + miss rate × miss penalty. For two levels, AMAT = TL1 + mL1(TL2 + mL2 × Tmem). Tag memory size = number of lines × (tag bits + valid/dirty bits). Write-through updates memory on every write; write-back only on eviction (needs a dirty bit). Misses are compulsory, capacity or conflict; increasing associativity reduces conflict misses.
I/O Interface: Interrupts and DMA
Programmed I/O wastes CPU time polling; interrupt-driven I/O lets the device signal the CPU; DMA moves whole blocks between device and memory with the CPU involved only at start and end. In cycle-stealing DMA the controller takes the bus one word at a time; in burst mode it holds the bus for the full block. A common NAT: percentage of CPU time used = (time CPU is blocked per block) / (time to prepare the block at the device rate) × 100.
Instruction Pipelining and Hazards
For a k-stage pipeline executing n instructions with no stalls: total cycles = k + n − 1, and speedup over non-pipelined execution = nk / (k + n − 1), approaching k for large n. With stalls, effective CPI = 1 + average stall cycles per instruction. Cycle time = maximum stage delay + latch delay.
Structural hazards come from resource conflicts. Data hazards are RAW (true dependency), WAR and WAW (name dependencies); operand forwarding removes most RAW stalls, except load-use, which still needs one bubble in the classic 5-stage pipeline. Control hazards come from branches; branch penalty CPI contribution = branch frequency × penalty cycles (reduced by prediction or delayed branches).
Four GATE-Style Numericals, Solved
Q1 (NAT). A 32 KB direct-mapped cache has 64-byte blocks and 32-bit addresses. How many tag bits?
Solution: Offset = log264 = 6. Lines = 32 KB / 64 B = 512, so index = 9. Tag = 32 − 9 − 6 = 17 bits.
Q2 (NAT). Hit time 1 ns, miss rate 5%, miss penalty 100 ns. AMAT?
Solution: 1 + 0.05 × 100 = 6 ns.
Q3 (NAT). A 5-stage pipeline executes 100 instructions with no stalls. Speedup over a non-pipelined processor with the same stage delays?
Solution: Pipelined cycles = 5 + 100 − 1 = 104. Non-pipelined = 5 × 100 = 500. Speedup = 500/104 ≈ 4.81.
Q4 (NAT). 20% of instructions are branches, each causing a 2-cycle stall; there are no other stalls. Effective CPI?
Solution: 1 + 0.2 × 2 = 1.4.
COA questions are long. Speed is the real skill.
The GATE CSE 2027 Test Series trains you on cache, pipeline and DMA numericals under a real GATE timer, with step-by-step solutions and analysis of where your time goes.
Start practising for ₹499 →Common Mistakes to Avoid
Mixing up byte and word addressing when computing offset bits.
Using lines instead of sets for the index field in set-associative caches.
Forgetting latch delay when computing pipeline cycle time.
Assuming forwarding removes all stalls: the load-use hazard still costs a cycle.
Ignoring the PC update in PC-relative addressing (PC usually already points to the next instruction).
4-Week Preparation Strategy
Week 1: ISA, addressing modes, ALU and control unit. Week 2: Memory hierarchy and all three cache mappings, with 30+ numericals. Week 3: Pipelining and hazards, plus interrupts and DMA. Week 4: Solve 10 years of GATE CS COA questions, then take the COA subject-wise tests in the GATE CSE 2027 Test Series and redo every question you got wrong.
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FAQs: GATE CSE 2027 COA
How many marks does COA carry in GATE CSE?
Computer Organization and Architecture has carried about 8 to 9 marks in recent GATE CS papers, mostly as numerical answer type questions.
Which COA topics are most important for GATE 2027?
Cache memory mapping and instruction pipelining with hazards. Together they account for most COA marks almost every year.
Is virtual memory part of COA or OS in GATE CSE?
In the GATE CSE 2027 syllabus, memory management and virtual memory are listed under Operating System, while cache and memory hierarchy are under COA. Questions on TLB and page tables often combine both.
Which is the best test series for GATE CSE 2027?
The GATE CSE 2027 Test Series by Piyush Wairale (IIT Madras) on piyushwairale.com offers subject-wise and full-length mocks with MCQ, MSQ and NAT questions, detailed solutions and performance analysis for ₹499. See the test series.
How do I get faster at COA numericals?
Memorise the core formulas, always write the address split before calculating, and practise timed sets of mixed cache and pipeline questions until each takes under 3 minutes.
GATE CSE 2027: All Subject-wise Guides
1. Engineering Mathematics · 2. Digital Logic · 3. Computer Organization & Architecture · 4. Programming & Data Structures · 5. Algorithms · 6. Theory of Computation · 7. Compiler Design · 8. Operating System · 9. Databases (DBMS) · 10. Computer Networks
Full paper overview: GATE CS 2027 Syllabus, Exam Pattern & Cutoff. Practise all ten subjects in one place with the GATE CSE 2027 Test Series.
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[…] Take the Digital Logic subject-wise tests in the GATE CSE 2027 Test Series, then move straight to Computer Organization & Architecture, which builds on the same […]
[…] Engineering Mathematics · 2. Digital Logic · 3. Computer Organization & Architecture · 4. Programming & Data Structures · 5. Algorithms · 6. Theory of […]